The present invention relates to self-aligned processing of a semiconductor device, and more particularly, but not exclusively relates to a technique to modify the gate of a field effect transistor structure by a self-aligned process.
Polysilicon is often the material of choice for the gates of field effect transistors formed on an Integrated Circuit (IC) because of its stability and compatibility with silicon processing technology. On the other hand, the relatively high electrical resistivity of polysilicon typically requires heavy doping and metallization in order to achieve acceptable performance. As the gate length continues to be scaled down, gate resistance becomes an increasingly significant factor limiting the circuit speed.
Gate metallization technologies have become an increasingly potent factor in meeting the challenges posed by shrinking gate dimensions. For example, self-aligned silicide techniques provide metallization in the form of a metal-silicon compound that is suitable in many cases. However, as device dimensions continue to decrease, the silicide metallization dimensions also typically decrease. When the silicide gate metallization becomes too thin, an unacceptably high sheet resistance usually results which is further complicated by narrow-linewidth effects for some silicide processes.
An ideal solution is to use a highly conductive material for the gate, such as an elemental metal, that would substantially lower sheet resistance and generally eliminate the narrow-linewidth problems posed by some silicide techniques. Unfortunately, the substitution of part or all of a polysilicon gate with an elemental metal significantly complicates conventional semiconductor processing. For example, most suitable metals would be unacceptably degraded by the chemicals and high temperatures (as high as 1000.degree. C.) encountered during the early stages of semiconductor device processing. This limitation generally precludes introduction of the metal as part of initial lithographic gate patterning. If the metal is introduced during later stages, a dedicated masking and lithography procedure to modify earlier patterned gates for the metal is typically required. With decreasing gate size, such a dedicated procedure is difficult to accurately align and execute.
Thus, there is a need for self-aligned processing of transistor gates. The present invention satisfies this need and provides other significant advantages.